The present invention relates to a semiconductor wafer. In particular, the present invention relates to a semiconductor wafer such as an SOS (Silicon On Sapphire) wafer having an insulation substrate with transparency.
In a manufacturing process of a semiconductor chip, when a semiconductor wafer is processed with a manufacturing device, it is necessary to confirm a presence of the semiconductor wafer on a side of the manufacturing device. In this case, a transmission type sensor is generally used for detecting the presence of the semiconductor wafer through light transmission or blocking light having a wavelength of 670 to 940 nm with an LED (Light Emitting Diode) as a light source.
In a case of a silicon (Si) wafer, there is no problem in detecting the semiconductor wafer with a transmission type sensor using light having a wavelength of 670 to 940 nm. Recently, however, an SOS (Silicon on Sapphire) wafer has been used for manufacturing a high-value added product such as an RF (Radio Frequency) device and the likes.
In the SOS (Silicon on Sapphire) wafer, a thin semiconductor layer is formed on a sapphire substrate. In a case of the SOS (Silicon on Sapphire) wafer, sapphire has transparency with respect to light having a wavelength of 670 to 940 nm, so that light transmits through the sapphire substrate. Accordingly, it is difficult to confirm a presence of the SOS (Silicon on Sapphire) wafer during a manufacturing process of a semiconductor chip.
In general, during a manufacturing process of a semiconductor chip, after a semiconductor element constituting a semiconductor chip is formed on the SOS (Silicon on Sapphire) wafer, a scribe line is formed in the SOS (Silicon on Sapphire) wafer, so that the semiconductor chip is cut into individual pieces. Normally, an alignment mark is formed on the scribe line for photolithography. Further, a TEG (Test Element Group) is formed on the scribe line for testing an electrical property of the semiconductor element.
Accordingly, an area of the SOS wafer is transparent other than areas where the scribe line, the alignment mark, and the TEG are formed. As a result, light transmits through the SOS wafer toward the transmission type sensor at a higher percentage. Therefore, even though the SOS wafer exists, it is difficult to confirm the presence of the SOS wafer during the manufacturing process of the semiconductor chip.
When it fails to confirm the presence of the SOS wafer, the SOS passes through a specific step without processing, thereby reducing a production yield and production efficiency of the semiconductor chips. In order to securely confirm the presence of the SOS wafer, a wavelength of light incident on the transmission type sensor may be adjusted, thereby confirming the presence of the SOS wafer at a high percentage.
Patent Reference has disclosed another technology for securely confirming the presence of the SOS wafer. In the technology, an outer contour portion having a width of about 5 mm is defined in an outer circumferential portion of the SOS wafer. Then, a photo resist mask is formed on a silicon semiconductor layer through photolithography, so that the outer contour portion is exposed. Ions are implanted into the silicon semiconductor layer in the outer contour portion with the photo resist mask as a mask, so that the silicon semiconductor layer in the outer contour portion becomes amorphous.
When the outer contour portion becomes amorphous, the outer contour portion becomes opaque. Accordingly, it is possible to securely confirm the presence of the SOS wafer. Patent Reference: Japanese Patent Publication No. 2005-223304
In the conventional technology described above, as compared with the case of detecting a semiconductor wafer with a transmission type sensor using light having a wavelength of 670 to 940 nm, it is possible to improve a recognition rate of the semiconductor wafer. However, the recognition rate of the SOS wafer is still not sufficient as opposed to that of the silicon wafer. Accordingly, it is still difficult to produce the semiconductor chip with a high yield, thereby reducing production efficiency of the semiconductor chip.
In the technology disclosed in Patent Reference, the outer contour portion disposed in the outer circumferential portion of the SOS wafer becomes amorphous and opaque. Accordingly, the outer contour portion is not utilized for producing the semiconductor chip, thereby reducing a chip forming area for forming the semiconductor chip. As a result, the number of the semiconductor chips produced from one SOS wafer decreases, thereby reducing production efficiency of the semiconductor chips.
In the technology disclosed in Patent Reference, it is necessary to provide an additional step for making the outer contour portion amorphous. Accordingly, it takes a longer period of time to produce the semiconductor chips, thereby increasing a production cost of the semiconductor chips.
In view of the problems described above, an object of the present invention is to provide and a semiconductor wafer capable of solving the problems of the conventional semiconductor wafer. In the semiconductor wafer, it is possible to improve a recognition rate of the semiconductor wafer such as an SOS wafer without reducing a chip forming area for producing a semiconductor chip.
Further objects and advantages of the invention will be apparent from the following description of the invention.